Principles of ASIC Design
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Follow on Instagram for UpdatesPrinciples of ASIC Design Syllabus — Unit-wise Content
The official GTU curriculum for Principles of ASIC Design (subject code ME02000951) as prescribed for VD · Semester 2 divides the course into 5 units, covering 46 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02000951)Unit 1 Introduction to ASIC
- Types of ASICs
- Design flow
- CMOS transistors
- CMOS Design rules
- Combinational Logic Cell
- Sequential logic cell
- Data path logic cell
- Transistors as Resistors
- Transistor Parasitic Capacitance
- Logical effort
- Library cell design
- Library architecture
Unit 2 PROGRAMMABLE ASICS, LOGIC CELLS AND I/O CELLS
- static RAM, EPROM and EEPROM technology
- PREP benchmarks
- Actel ACT, Xilinx LCA, Altera FLEX
- Altera MAX DC & AC inputs and outputs
- Clock & Power inputs
- Xilinx I/O blocks
Unit 3 PROGRAMMABLE ASIC INTERCONNECT AND DESIGN SOFTWARE
- Actel ACT, Xilinx LCA, Xilinx EPLD
- Altera MAX 5000 and 7000
- Altera MAX 9000
- Altera FLEX
- Design systems
- Logic Synthesis
- Half gate ASIC
- Schematic entry
- Low level design language
- PLA tools
- CFI design representation
Unit 4 FPGA ARCHITECTURES, SIMULATION AND TESTING
- FPGA Architectures
- SRAM-Based FPGAs
- Permanently Programmed FPGAs
- Types of simulation
- boundary scan test
- Fault simulation
- Automatic Test Pattern Generation
- Introduction to JTAG
Unit 5 PHYSICAL DESIGN OF ASIC
- System partition
- FPGA partitioning
- partitioning methods
- floor planning
- physical design flow
- global routing
- detailed routing
- special routing
- circuit extraction, DRC
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