Mixed Signal CMOS Circuit Design

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MIXED SIGNAL CMOS ME02000161
FREE PDF ME02000161
Code: ME02000161 Credits: 4 Semester 2 VD

Mixed Signal CMOS Circuit Design

Get the full GTU study material, English & Gujarati textbook PDFs, syllabus curriculum, and solved previous year question papers.

Mixed Signal CMOS Circuit Design Syllabus — Unit-wise Content

The official GTU curriculum for Mixed Signal CMOS Circuit Design (subject code ME02000161) as prescribed for VD · Semester 2 divides the course into 7 units, covering 53 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.

Download the official syllabus PDF (ME02000161)

Unit 1 Nanometer Design Studies

4 lecture hours

  • Transistor Design Considerations
  • Deep-Submicron Effects
  • Transconductance Scaling
  • Transistor Design
  • Op Amp Design Examples
  • High-Speed Amplifier

Unit 2 Bandgap References

6 lecture hours

  • General Considerations
  • Supply-Independent Biasing
  • Temperature- Independent References
  • Negative-TC Voltage
  • Positive-TC Voltage
  • Bandgap Reference
  • PTAT Current Generation
  • Constant-Gm Biasing
  • Speed and Noise
  • Low-Voltage Bandgap References
  • Case Study

Unit 3 Introduction to Switched-Capacitor Circuits

7 lecture hours

  • General Considerations
  • Sampling Switches
  • MOSFETS as Switches
  • Speed Considerations
  • Precision Considerations
  • Charge Injection Cancellation
  • Switched-Capacitor Amplifiers
  • Unity-Gain Sampler/Buffer
  • Noninverting Amplifier
  • Precision Multiply-by-Two Circuit
  • Switched-Capacitor Integrator
  • Switched-Capacitor Common-Mode Feedback

Unit 4 Oscillators and Phase-Locked Loops (PLLs)

6 lecture hours

  • Ring Oscillators
  • LC Oscillators
  • Cross-Coupled Oscillator
  • Colpitt Oscillator
  • Voltage-Controlled Oscillators Phase-Locked Loops: Simple PLL, Charge-Pump PLLs
  • Problem of Lock Acquisition
  • Non-ideal Effects in PLLs

Unit 5 Nonlinear Analog Circuits

5 lecture hours

  • Basic CMOS Comparator Design
  • Characterizing the Comparator
  • Clocked Comparators
  • Adaptive Biasing
  • Analog Multipliers

Unit 6 Data Converter Fundamentals and Architectures

12 lecture hours

  • Sample-and-Hold (S/H) Characteristics
  • Specifications of Digital-to- Analog Converter (DAC) and Analog-to-Digital Converter (ADC)
  • Mixed- Signal Layout Issues
  • DAC Architectures: R-2R Ladder Networks
  • Current Steering
  • Charge-Scaling DACs
  • Cyclic DAC, Pipeline DAC, ADC Architectures: Single and Two-step Flash
  • Pipeline ADC, Integrating ADCs
  • Successive Approximation ADC, Oversampling ADC

Unit 7 Implementing Data Converters

6 lecture hours

  • R-2R Topologies for DACs
  • Implementing ADCs: Implementing the S/H
  • Cyclic ADC, Pipeline ADC

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