Design of Low Power CMOS Circuits
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Follow on Instagram for UpdatesDesign of Low Power CMOS Circuits Syllabus — Unit-wise Content
The official GTU curriculum for Design of Low Power CMOS Circuits (subject code ME02000091) as prescribed for VD · Semester 2 divides the course into 5 units, covering 76 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02000091)Unit 1 Introduction to Low Power Issues in VLSI
- Switching Power Consumption
- Short – circuit Power Consumption
- leakage Power Consumption
- Low Power IC Design beyond Sub-20 nm Technology
- Issues Related to Silicon Manufacturability and Variation
- Issues Related to Design Productivity
- Limitation Faced by CMOS
- International Technology Roadmap for Semiconductors
- Different Groups of MOSFETs
- Three MOS Types
- Low Leakage MOSFET
- Importance of Subthreshold Slope
- Why Is Subthreshold Current Exponential in Nature?
- Subthreshold Leakage and Voltage Limits
- Importance of Subthreshold Slope in Low Power Operation
- Ultralow Voltage Operation
- Low Power Analog Circuit Design
- Fundamental Consequence of Lowering Supply Voltage
- Analog MOS Transistor Performance Parameters
Unit 2 Scaling and Short Channel Effects in MOSFET
- MOSFET Scaling
- Influence of voltage scaling on Power and Delay
- VTCMOS circuits
- MTCMOS circuits
- Gate Oxide Scaling
- Gate Leakage Current
- High-k Gate Dielectrics
- Key Guidelines for Selecting an Alternative Gate Dielectric
- Gate Tunneling Current
- Gate Length Scaling
- Introduction to Short Channel Effect in MOSFET
- Reduction of Effective Threshold Voltage
- Drain-induced Barrier Lowering
- Mobility Degradation and Surface Scattering
- Surface Scattering
- Hot Carrier Effect
- Punch- through Effect
- Velocity Saturation Effect
- Increase in Off-state Leakage Current
- Lightly Doped Drain Structure
- Channel Engineering Technique
- Gate Engineering Technique
- Single Halo Dual Material Gate MOSFET
- Double Halo Dual Material Gate MOSFET
- Double Gate MOSFET
- Dual Material Double Gate MOSFET
- Triple Material Double Gate MOSFET
- Triple Gate MOSFET
- Gate-all-around MOSFET
- Surrounding Gate MOSFET
- Silicon Nanowires
- Fringing-induced Barrier Lowering
- Silicon-on- insulator MOSFETs
Unit 3 Advanced Energy-reduced CMOS Inverter Design
- Transfer Characteristics of Inverter
- Static CMOS Inverter in Super- threshold Regime
- Introduction to Subthreshold Logic
Unit 4 Advanced Combinational Circuit Design
- Static CMOS Logic Gate Design
- Complementary Properties of CMOS Logic
- Pseudo-nMOS Gates
- Sizing of Transistor in CMOS Design Style
- Introduction to Logical Effort
- Delay Estimation by Program Name: Master of Engineering Level : PG Subject Code : ME02000091 Subject Name : Design of Low Power CMOS Circuits w.e.f 2024-25 http:// syllabus.gtu.edu.in / Page 3 of 4 Logical Effort
- Tristate Buffer
- Transmission Gates and Tristates
- Implementation of Combinational Circuit Using DTMOS Logic for Ultralow Power Application
- ECLR Structure
- Power Consumption
- Propagation Delay
Unit 5 Advanced Energy-reduced Sequential Circuit Design
- Basics of Regenerative Circuits
- Basic SR Flip-flop/Latch
- Clocked JK Latch
- Master–slave Flip-flop
- Master–slave Edge-triggered Flip-flops
- Timing Parameters for Sequential Circuits
- Clock Skews due to Non-ideal Clock Signal
- Design and Analysis of the Flip-flops Using DTMOS Style
- Adiabatic Flip-flop
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