Testing and Verification of VLSI Design
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Follow on Instagram for UpdatesTesting and Verification of VLSI Design Syllabus — Unit-wise Content
The official GTU curriculum for Testing and Verification of VLSI Design (subject code 2724202) as prescribed for EAC( · Semester 2 divides the course into 13 units, covering 76 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (2724202)Unit 1 Introduction of Testing and Verification
- Testing Philosophy
- Roll Of Testing
- Digital And Analog VLSI Testing
- VLSI Technology Trends Effecting Testing
- Verification Importance
- Reconvergence Model
- The Human Factor
- What Is Being Verified? Verification and Design Reuse
- The Cost Of Verification
- Testing Versus Verification
Unit 2 Test Process and Equipment
- How To Test Chips? Types Of Testing
- Automatic Test Equipment
- Electrical Parametric Testing
Unit 3 Test Economics and Product Quality
- Test Economics
- Defect Level As A Quality Measure
Unit 4 Fault Modeling
- Errors, And Faults
- Functional Versus Structural Testing
- Levels Of Fault Models
- A Glossary Of Fault Models
- Single Stuck-At Fault
Unit 5 Fault Simulation
- Usage of fault simulators
- Fault simulator in a VLSI design process
- Fault simulation algorithms: Serial
- Fault sampling
Unit 6 Combinational ATPG
- Structural vs. functional test
- Definition of ATPG
- Exhaustive algorithm
- Random pattern generation
- Boolean difference 3symbolic method
- Path sensitization method
- Computation complexity
Unit 7 Design-for-Testability
- Ad-hoc DFT methods
- Scan design
- Scan flip-flop
- Scan test vectors
- Multiple scan registers
- Hierarchical scan
Unit 8 Verification Tools
- Linting Tools
- Third-Party Models
- Waveform Viewers
- Code Coverage
- Verification Languages
- Revision Control
- Issue Tracking
Unit 9 The Verification Plan
- The Role of the Verification Plan
- Levels of Verification
- Verification Strategies
- From Specification to Features
- From Features to Testcases
- From Testcases to Test benches
Unit 10 Delay Test
- Delay test problem
- Path delay test
- Transition Faults
- Delay test methodologies
- Test and diagnosis for Small-Delay Defects (SDDs)
Unit 11 IDDQ Current Testing
- History and motivation
- Basic principle of IDDQ testing
- Fault detected by IDDQ tests
- Limitations of IDDQ testing
Unit 12 Memory Testing
- Functional model of a memory
- Fault models
- March tests
Unit 13 Built-In Self-Test
- BIST definitions
- BIST process
- BIST pattern generation
- BIST response compaction
- Aliasing definition References: 1
- V.D.Agrawal “Essentials of Electronic testing for Digital
- Memory and Mixed Signal VLSI Circuits”
- Kluwer Academic Publishers
- New York
- Janick Bergeron
- “Writing test benches functional verification of HDL models” Kluwer Academic Publishers
- Jayaram Bhasker “A VHDL Primer”
- P T R Prentice Hall Englewood Cliffs
- New Jersey
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