Unit 1 Introduction

5 lecture hours

• Design Methodology
• Level of Abstractions
• Design Flow
• Design Approaches
• Design Styles
• Design considerations
• Design Qualities
• EDA tools

Unit 2 Introduction to HDL Based Design

4 lecture hours

• Digital System Implementation options and selection criteria
• HDL based design flow

Unit 3 VHDL

9 lecture hours

• VHDL Based Digital Design Flow
• VHDL for Library
• VHDL Concurrent and Sequential Syntax
• Language Elements
• Different style of modellig
• Designing Combinational Language Logic and Synchronous Logic

Unit 4 Programmable Logic Devices

10 lecture hours

• Full Custom Design
• Semicustom Design
• Programmable Logic Devices
• Read Only Memory (ROM)
• Programmable Read Only Memory (PROM), and Programmable Logic Array (PLA), and Programmable Array Logic (PAL)
• CPLD Architecture & CPLDs available in Market
• FPGA Architectures
• New trends in FPGAs
• Selection Criteria and comparative study of all available programmable logic

Unit 5 State Machine Design

• State Machine Modelling
• Modelling a Moore FSM, Modelling a Mealy FSM 5 10

Unit 6 Simulation and Synthesis

9 lecture hours

• Event-driven simulation
• Cycle Based Simulator
• Writing a test bench
• A test bench example
• Simulation modelling issues
• What is synthesis
• Synthesis in a Design Process RTL synthesis
• Modelling for Synthesis versus Modelling for Simulation
• Behavioral synthesis

Unit 7 Verilog

• Different style of modeling. 6 13