Memory Technology
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Follow on Instagram for UpdatesMemory Technology Syllabus — Unit-wise Content
The official GTU curriculum for Memory Technology (subject code ME02000961) as prescribed for EAC( · Semester 2 divides the course into 5 units, covering 37 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02000961)Unit 1 Introduction
- Overview of memory technologies
- Memory organization
- trends and technologies. 4 5 Mainstream Semiconductor Memory Technologies : A
- Volatile Memories :
Unit 2 Static Random Access Memory (SRAM)
- SRAM Cell Structures
- MOS SRAM Architecture
- 6-T MOS SRAM Cell
- CMOS SRAM Cell Design Strategy
- Noise margin
- Scaling issues Read and Write circuitry
- Sense amplifier
- Advanced SRAMArchitectures
- Application Specific SRAMs
Unit 3 Dynamic Random Access Memory (DRAM)
- 3-T DRAM operation
- Read-Write Circuits
- 1T-1C DRAM Cell Fabrication technology and capacitor structure
- Soft Error Failures in DRAMsAdvanced DRAM Designs and Architecture-Application Specific DRAMs
- Non-volatile Memories :
Unit 4 Masked ROMs, CMOS PROM, EEPROMs, Floating Gate EPROM
- Flash Memories: NAND v/s NOR architecture
- Scaling, and Multi-Level Cell capability (MLC)
- Advanced Flash Memory Architectures Emerging Memory Technologies :
Unit 5 Resistive RAM (RRAM), Phase Change Memory (PCM), Ferroelectric
- RAM (FeRAM)
- Conductive Bridge RAM (CBRAM)
- Magneto- resistive RAMs: Spin-Transfer Torque MRAM (STT-MRAM) and Spin-Orbit Torque MRAM (SOT-MRAM)
- Comparative analysis of all eNVMs
- Unconventional Applications of eNVMs: Neuromorphic Computing
- Computing-inMemory (CiM)
- Memory Hybrids (2D & 3D)
- Memory Stacks
- Memory Testing and Reliability Issues
- High Density Memory Packaging 9 25 Memory Fault Modeling and Design for Testability : RAM Fault Modeling
- Electrical Testing
- Pseudo Random Testing
- Megabit DRAM Testing
- Nonvolatile Memory Modeling and Testing
- IDDQ Fault Modeling and Testing
- Memory Built-In Self -Test (MBIST)