VLSI Test Principles and Architectures
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Follow on Instagram for UpdatesVLSI Test Principles and Architectures Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Test Principles and Architectures (subject code ME02096051) as prescribed for EACD · Semester 2 divides the course into 5 units, covering 66 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02096051)Unit 1 Introduction
- Importance of testing
- testing during the VLSI lifecycle
- Challenges in VLSI testing
- levels of abstraction in VLSI testing
- historical review of VLSI test technology
- Program Name: Master of Engineering Level: PG Branch: Electronics And Communication (VLSI Design) Subject Code: ME02096051 Subject Name: VLSI Test Principles and Architectures
Unit 2 Design for Testability
- testability analysis
- design for testability basics
- scan architecture
- scan design rules
- special-purpose scan designs
- RTL design for testability
Unit 3 Logic and Fault Simulation
- simulation models: Gate-level network
- logic symbols
- logic element evaluation
- timing models
- Logic Simulation: compiled-code simulation
- event-driven simulation
- compiled- code Vs event-driven simulation
- Fault simulation: serial fault simulation
- parallel fault simulation
- deductive fault simulation
- concurrent fault simulation
- differential fault simulation
- fault detection
- comparison of fault simulation techniques
- alternatives to fault simulation
Unit 4 Test Generation
- random test generation
- theoretical background: Boolean difference
- designing a Stuck-At ATPG for combinational circuits: A naïve ATPG algorithm
- a basic ATPG algorithm
- PODEM, FAN, static logic implication
- dynamic logic implications
- Designing a sequential ATPG: time frame expansion
- 5- valued algebra Is insufficient
- gated clocks and multiple clocks
- Unstable faulty identification
- Designing a simulation-based ATPG
- Advanced simulation-based ATPG
- hybrid deterministic and simulation-based ATPG
- ATPG for Non-Stuck-At faults
- other topics in Test Generation
Unit 5 Logic Built-In Self-Test
- BIST design rules: unknown source blocking
- Test Pattern Generation: exhaustive testing
- pseudo-random testing
- pseudo-exhaustive testing
- delay fault testing
- Output Response Analysis: one count testing
- transition count testing
- signature analysis
- Logic BIST Architectures: BIST architectures for circuits without scan chains
- BIST architectures for circuits with scan chains
- BIST architectures using register reconfiguration
- modified Built-In logic block observer
- concurrent Built-In logic block observer
- BIST architecture using concurring checking circuits: concurrent self- verification
- Fault Coverage Enhancement: test point insertion
- mixed- mode BIST
- hybrid BIST
- BIST Timing Control: single-capture
- skewed- load
- fault detection
- A Design Practice: BIST rule checking and violation repair
- logic BIST system design
- RTL BIST synthesis
- design verification and faulty coverage
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