Semiconductor Memory Circuits Design
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Follow on Instagram for UpdatesSemiconductor Memory Circuits Design Syllabus — Unit-wise Content
The official GTU curriculum for Semiconductor Memory Circuits Design (subject code ME02096031) as prescribed for EACD · Semester 2 divides the course into 5 units, covering 75 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02096031)Unit 1 Random Access Memory Techniques
- static random-access memories (SRAMs): SRAM (NMOS and CMOS cell structures
- MOS SRAM architectures
- MOS SRAM cell and peripheral circuit operation
- bipolar SRAM technologies
- Silicon-on-Insulator (SCI) technology
- advanced SRAM architectures and technologies
- application-specific SRAMS
- Dynamic Random-Access Memories (DRAMs)
- DRAM technology development
- CMOS DRAMs
- DRAM cell theory and advanced cell structures
- BiCMOS DRAMs
- soft-error failures in DRAMS
- advanced DRAM designs and architectures
- a 16-Mb DRAM
- ULSI DRAM developments
- Application-Specific DRAMs: Pseudo static DRAMS
- silicon file
- video DRAMS
- high-speed DRAMs
- application-specific RAM glossary and summary
Unit 2 Nonvolatile Memories
- Masked Read-Only memories (ROMs): technology development and cell programming
- ROM cell structures
- high-density ROMs
- Programmable Read-Only memories (PROMs): bipolar PROMs
- CMOS PROMs
- Erasable -Programmable Read- Only Memories (EPROMs): floating-gate EPROM cell
- EPROM technology developments
- advanced EPROM architectures
- OTP EPROMS
- Electrical Erasable PROMS (EEPROMs): EEPROM technologies
- EEPROM architectures
- nonvolatile SRAM
- Flash memories (EPROMs/EEPROMs): flash memory cells and technology developments
- advanced flash memory architectures
Unit 3 Memory Fault Modeling and Testing
- RAM fault modeling: stuck-at faulty model
- bridging faults
- coupling faults
- pattern-sensitive faults
- miscellaneous faults
- GaAs SRAM fault modeling and testing
- embedded DRAM faulty modeling and testing
- RAM Electrical Testing: DC and AC parametric testing
- functional testing and some commonly used algorithms
- functional test pattern selection
- RAM pseudorandom testing
- megabit DRAM testing
- nonvolatile memory modeling and testing: DC electrical measurements
- AC and functional measurements
- IDDQ fault modeling and testing
- application specific memory testing
Unit 4 Memory Design for Testability and Faulty Tolerance
- general design for testability techniques: Ad Hoc design techniques
- structured design techniques
- RAM Built-In Self-Test (BIST): BIST using algorithmic test sequence
- BIST using 13N March algorithm
- BIST for pattern-sensitive faults
- BIST using BILBO
- Embedded memory DFT and BIST techniques
- Advanced BIST and Built-In Self-Repair architectures
- DFT and BIST for ROMs
- memory error detection and correction techniques
- memory fault- tolerance designs Program Name: Master of Engineering Level: PG Branch: Electronics And Communication (VLSI Design) Subject Code: ME02096031 Subject Name: Semiconductor Memory Circuits Design
Unit 5 Advanced Memory Technologies
- Ferroelectric RAMs (FRAMS): basic theory
- FRAM cell and memory operation
- FRAM technology developments
- FRAM reliability issues
- FRAM radiation effects
- FRAMS Vs EEPROMs
- GaAs FRAMS
- analog memories
- magnetoresistive RAMs (MRAMs)
- experimental memory devices: quantum-mechanical switch memories
- a GaAs n-p-n-p Thyristor/JFET memory cell
- single electron memory
- neuron-MOS multiple-valued memory technology. 6 10
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