CMOS Digital Circuit Design
Get the full GTU study material, English & Gujarati textbook PDFs, syllabus curriculum, and solved previous year question papers.
English Book & Chapters
English Book Coming Soon
We are working hard to add this material. Stay tuned for updates!
Follow on Instagram for UpdatesGTU Previous Year Papers
Papers Coming Soon
We are working hard to add this material. Stay tuned for updates!
Follow on Instagram for UpdatesCMOS Digital Circuit Design Syllabus — Unit-wise Content
The official GTU curriculum for CMOS Digital Circuit Design (subject code ME01096031) as prescribed for EACD · Semester 1 divides the course into 6 units, covering 25 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME01096031)Unit 1 MOS Inverter – Switching Characteristics and Interconnect
- Effects: Introduction
- delay-time definitions
- calculation of delay times
- inverter design with delay constraints
- estimation of interconnect parasitic
- calculations of interconnect delay
- switching power Program Name: Master of Engineering Level: PG Branch: Electronics And Communication (VLSI Design) Subject Code: ME01096031 Subject Name: CMOS Digital Circuits Design dissipation of CMOS inverters
Unit 2 Combinational MOS Logic Circuits
- MOS logic circuits with depletion nMOS loads
- COMS logic circuits
- complex logic circuits
- CMOS transmission gates
Unit 3 Sequential MOS Logic Circuits
- behavior of bistable elements
- the SR latch circuit
- clocked latch and flip-flop circuits
- CMOS D-latch and edge-triggered flip-flop
Unit 4 Semiconductor Memories
- read-only memory circuits
- static read-write memory circuits
- dynamic read-write memory circuits
Unit 5 Arithmetic Building Blocks
- Architectures of Adders
- Subtractors, and Multipliers. 7 15
Unit 6 Low-Power CMOS Logic Circuits
- overview of power consumptions
- low-power design through voltage scaling
- estimation and optimization of switching activity
- reduction of switched capacitance
- adiabatic logic circuits. 7 15