Standard Cell Library & Memory Design
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Follow on Instagram for UpdatesStandard Cell Library & Memory Design Syllabus — Unit-wise Content
The official GTU curriculum for Standard Cell Library & Memory Design (subject code 3735202) as prescribed for EAC( · Semester 3 divides the course into 5 units, covering 41 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3735202)Unit 1 Introduction
- IC design flows
- Use of standard cell elements vs. custom design and Gate array paradigms
- Introduction to memory types and construction of memory elements
Unit 2 Standard cell library composition and usage
- Types of standard cell elements
- Logical and functional elements
- primitives and complex macros
- Sequential elements and register files
- (Flip flop and latch design)
- Data path elements
- Library size vs. usage in standard flows
- Drive strength and cell families
- Layout of library elements – single height
- double height cells
- Power Management cells
Unit 3 Standard cell characterization
- Usage of standard cells by various tools
- Information needed at each stage of design flow
- Characterization parameters
- setup and runs across PVT corners
- Library representation formats
- (Gate level simulation
- timing, LVS, DRC)
Unit 4 Memory elements and array design
- Volatile and Non-volatile RAM, ROM, EPROM
- Flash (EEPROM)
- OTP elements and cell design
- State retention volatile memories
- Array design – architecture
- bitline/wordline optimization
- sense-amps and mux/demux architecture
- Memory banking
- refresh cycle management
- Multi-port memories
- Cache memories
- Special memories such as CAMs
Unit 5 Memory defects, failures and testing, layout and characterization
- Memory defects and repair
- Temporal failures
- Soft errors
- Membist and other test techniques for memories
- Memory layout and its impact on performance
- Characterization of memories – timing
- power parameters
- Layout views
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