Design for Testability
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Follow on Instagram for UpdatesDesign for Testability Syllabus — Unit-wise Content
The official GTU curriculum for Design for Testability (subject code 3735201) as prescribed for EAC( · Semester 3 divides the course into 4 units, covering 36 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3735201)Unit 1 Introduction
- The need for testing
- Assembly and Test Process Flows
Unit 2 Scan Testing
- Using additional primary inputs and outputs to improve controllability and observability
- Scan-based testing
- Design rules
- Ways to overcome rule violations
- Automated Test Pattern Generation for scan testing
- Scan test protocol
- Full-scan and partial scan
- Automated scan design systems
- Scan design flow
- Scan design overhead: area
- power considerations
Unit 3 Built-in self-testing (BIST)
- BIST architecture
- Test compression methods
- Random and weighted random pattern testability
- BIST Pattern generator and response analyzer
- Theory of Linear feedback shift registers (LFSR)
- Generating test vectors and Signature analysis
- Scan-based BIST architecture
- Built-in Logic Block Observation (BILBO)
- Test point insertion for improving random testability
- Memory IC BIST and Built-In self-repair
Unit 4 Boundary Scan Testing
- Boundary scan technique
- JTAG standard (IEEE 1149.1)
- Application of Boundary scan for PCB testing
- Boundary scan instructions
- Boundary Scan Description Language (BCDL)
- Boundary scan Test access port (TAP)
- TAP controller
- Instruction register
- Test data register
- Boundary scan register
- TAP controller state diagram
- Testable design flow
- Using Boundary scan TAP for IC internal circuit testing
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