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SYSTEM ON CHIP 3725205

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Code: 3725205 Credits: 5 Semester 2 EAC(

System on Chip Architecture (Elective)

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System on Chip Architecture (Elective) Syllabus — Unit-wise Content

The official GTU curriculum for System on Chip Architecture (Elective) (subject code 3725205) as prescribed for EAC( · Semester 2 divides the course into 4 units, covering 32 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.

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Unit 1 SoC methodology

6 lecture hours

Abstract system modeling – Introduction to Transaction Level Modeling(TLM)
High Level Synthesis (HLS)
Requirement analysis related to power
performance and cost – Algorithms
implementation constraints
control and data path analysis
interfacing requirements
Integration and Verification
Regression testing Part – I System on FPGA

Unit 2 Embedded hard and soft processor cores in FPGAs from Altera, Xilinx and

6 lecture hours

Interfacing processor core with user FPGA logic
IP cores and interface to processor bus, Booting methods
configuration and parametric customization
design environment
base system builder
hardware simulation flow
supported OS and porting effort
Processor bus bridging to support reusable IPs/peripherals
Case study- AXI4 bus specification
Memory organization – Internal and external memory controller design
cross- compilers for HLL programming
provision for custom instructions
Auxiliary processing units

Unit 3 Xilinx Zynq family overview, system development methodology, use of the

6 lecture hours

ARM processor features like Neon, MMU, floating point unit
exception handling
Developing AXI4 based peripheral using FPGA fabric Part – II System on Chip

Unit 4 Requirement analysis, Classification of SoC, Comparative study of

6 lecture hours

different SoC platforms from TI, freescale
ezchip and more etc…- Key features
accelerator engines
application domains like graphics, DSP, image processing
audio-video encoding-decoding
Power efficiency
performance criteria

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System on Chip Architecture (Elective)

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System on Chip Architecture (Elective) Syllabus — Unit-wise Content

Unit 1 SoC methodology

Unit 2 Embedded hard and soft processor cores in FPGAs from Altera, Xilinx and

Unit 3 Xilinx Zynq family overview, system development methodology, use of the

Unit 4 Requirement analysis, Classification of SoC, Comparative study of

More Subjects in Semester 2

Systems Design

Protocols and Interfaces

Digital VLSI Design - II Backend

Designing with Modelling & FPGAs

System on Chip Architecture

Analog and Mixed Signal IC Design

Wireless Technology for Embedded Systems

Device Drivers - I

Systems Design Lab

Elective Subject Lab1

Elective Subject Lab2

System Design

Protocols and Interfaces

Digital VLSI Design - II Backend (Elective)

Designing with Modelling & FPGA s (Elective)

Analog and Mixed Signal IC Design (Elective)

Wireless Technology for Embedded Systems (Elective)

Device Drivers - I (Elective)

System Design(Practical)

Digital VLSI Design - II Backend (Practical)

System on Chip Architecture (Practical)

Analog and Mixed Signal IC Design (Practical)

Wireless Technology for Embedded Systems (Practical)

Device Drivers -I (Practical)

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