Digital VLSI Design - II Backend (Elective)
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Follow on Instagram for UpdatesDigital VLSI Design - II Backend (Elective) Syllabus — Unit-wise Content
The official GTU curriculum for Digital VLSI Design - II Backend (Elective) (subject code 3725203) as prescribed for EAC( · Semester 2 divides the course into 4 units, covering 48 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3725203)Unit 1 Recap of Front-end flow and Logic Synthesis
- Recap Units II and IV of Course Digital VLSI Design I – Front-end
Unit 2 Physical Design Setup and Floor planning
- VLSI Design Cycle
- Methodology of Physical Design
- Simplified Cycle of Physical IC Design
- Floor planning
- Logical libraries
- Physical Libraries
- Timing Constraints
- Database format
- Logical data setup
- Physical data setup
- Technology Files
- Interconnect delay models
- tcl scripting for automation
- Hierarchical Design Planning Flow
- Pad Creation and Order Assignments
- Core Area
- Initializing the Floorplan
- Timing Driven Placement
- Placement with Hierarchical Gravity
- Analyze placement and Color Modules
- Post- initialization Macro placement controls
- Large Macro Handling
- Power Network Synthesis (PNS)
- Power Network Analysis (PNA)
Unit 3 Placement
- Placement Methodology
- Fast Iteration with Coarse Placement
- Understanding the Congestion Calculation
- Textual Congestion Report
- Analyzing the Congestion Map, Global Route (GR) for Congestion Map, Strategies for Fixing Congestion Problems
- Congestion-Driven Placement Options
- Adjusting Cell Density
- Timing and Power Optimization for Best QoR, Congestion-Driven Placement
- Incremental Congestion Refinement
- Refinement Flow
- Incremental mode
- Area Recovery
- Timing Analysis
Unit 4 Clock Tree Synthesis
- Design Status
- Start of CTS Phase
- Clock Tree Synthesis
- CTS Goals
- Define Clock Root Attributes
- Float and Exclude Pins
- Generated and Gated Clocks
- User-defined or Explicit Stop Pins
- Defining an Explicit Float Pin, Preserving Pre-Existing Clock Trees
- Impact of Preexisting Clock Cells
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