Designing with Modelling & FPGAs
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Follow on Instagram for UpdatesDesigning with Modelling & FPGAs Syllabus — Unit-wise Content
The official GTU curriculum for Designing with Modelling & FPGAs (subject code 2725204) as prescribed for EAC( · Semester 2 divides the course into 6 units, covering 76 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (2725204)Unit 1 Review of transistor operation, Single stage amplifiers, Differential amplifier
- MOS I/V characteristics
- Transistor second order effects
- Small signal analysis
- Small signal model.Gain of common-source stage amplifier using small signal analysis
- Common-source stage with resistive load
- diode-connected load
- current-source load
- triode load
- source degeneration
- Source follower stage
- Common-gate stage
- Cascode stages.Single-ended and differential operation
- Basic differential pair.Common-mode response
- Differential pair with MOS loads
- Gilbert Cell
Unit 2 Current Mirrors, Response of Amplifiers, Noise characteristics
- Basic and cascode current mirrors
- Using active current mirrors as loads
- The Miller theorem
- Frequency response of source follower
- common-gate amplifier
- cascode stage
- differential pair.Noise characteristics
- Noise types: thermal noise
- flicker noise
- Representation of noise in circuits
- Properties of feedback circuits
- Feedback Configurations
- Effect of loading in feedback
Unit 3 Operational amplifiers
- Operational amplifier’s performance parameters
- One-Stage Op Amps
- Two-Stage Op Amp
- Op Amps Gain Boosting
- Op Amps Common-Mode Feedback
- Op Amps Input Range Limitation: unity-gain buffer
- extension of input CM range
- variation of equivalent transconductance with the input CM level
- Op Amps Slew Rate
- Noise in Op Amps and Power Supply Rejection.Stability and Frequency compensation
Unit 4 Bandgap References, Switched-capacitor circuits,Nonlinearity
- Supply-independent biasing
- Temperature- independent references: negative-TC voltage
- positive-TC voltage
- bandgap reference
- PTAT current generation
- Speed and noise issues
- Continuous-time feedback amplifier using resistors
- switched-capacitor amplifier in sampling mode
- amplification mode
- transfer of capacitor’s charges
- Sampling switches
- Switched-capacitor amplifiers
- Switched-capacitor integrator
- Ring oscillators
- LC oscillators
- Voltage-controlled oscillators
- Mathematical models of VCOs
Unit 5 Phase-locked loops, Data converters, charge-coupled devices (CCD)
- Simple PLL.Charge-pump PLLs.Non ideal effects in PLLs: PFD/CP non idealities
- jitter in PLLs.Delay-locked loops.PLL applications
- Analog versus discrete time signals
- Sample and hold characteristics.ADC and DAC specifications.DAC architectures.ADC architectures
- Sampling and aliasing
- Quantization noise & Data Converter SNR
- CCD imaging and architecture
Unit 6 Modeling with FPGA
- Logic modeling – Memory modeling
- Bus Function Modeling (BFMs)
- System modeling- Proof of Concept
- Timed and untimed functions and their interactions, TLM, IP core models and simulation
- Synthesizable modeling
- Case studies – Parameterized Flip-Flop
- DDR/QDR Memory Labs: Tools used during laboratory exercises are Custom Designer
- WaveView and HSpice
- Circuit design
- Layout, and Simulation (2nd Edition)
- Electronic Circuit Design: Art and Practice
- Design of Analog CMOS Integrated Circuits
- CMOS Mixed-Signal Circuit Design
- Principles of Data Conversion System Design. 1994. 272P
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