Unit 1 Programmable DSP Hardware

6 lecture hours

•  Processing Architectures (von Neumann
• Harvard)  DSP core algorithms (FIR, IIR, Convolution
• FFT)  IEEE standard for Fixed and Floating Point Computations  Special Architectures Modules used in Digital Signal Processors (like MAC unit
• Barrel shifters)  On-Chip peripherals  DSP benchmarking

Unit 2 Structural and Architectural Considerations

22 lecture hours

•  Parallelism in DSP processing  Texas Instruments TMS320 Digital Signal Processor Families  Fixed Point TI DSP Processors:TMS320C1X and TMS320C2X Family  TMS320C25 –Internal Architecture
• Arithmetic and Logic Unit
• Auxiliary Registers
• Addressing Modes (Immediate
• Direct and Indirect
• Bit-reverse Addressing)  Basics of TMS320C54x and C55x Families in respect of Architecture improvements and new applications fields  TMS320C5416 DSP Architecture
• Memory Map, Interrupt System
• Peripheral Devices  Illustrative Examples for assembly codingation (EMIF)

Unit 3 VLIW Architecture

• 7 17%  Current DSP Architectures  GPUs as an alternative to DSP Processors  TMS320C6X Family
• Addressing Modes  Replacement of MAC unit by ILP  Detailed study of ISA  Assembly Language Programming
• Code Composer Studio
• Mixed C and Assembly Language programming  Simple applications developments as an embedded environment

Unit 4 FPGA based DSP Systems

7 lecture hours

•  Limitations of P-DSPs  Requirements of Signal processing for Cognitive Radio (SDR)  FPGA based signal processing design-case study of a complete design of DSP processor