DSP Architecture
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Follow on Instagram for UpdatesDSP Architecture Syllabus — Unit-wise Content
The official GTU curriculum for DSP Architecture (subject code ME01000351) as prescribed for EAC( · Semester 1 divides the course into 5 units, covering 42 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME01000351)Unit 1 Programmable DSP Hardware
- Processing Architectures (Von Neumann
- DSP core algorithms (FIR, IIR, Convolution
- IEEE standard for Fixed and Floating Point Computations
- Special Architectures Modules used in Digital Signal Processors (like MAC unit
- Barrel shifters)
- On-Chip peripherals
- DSP benchmarking
Unit 2 Structural and Architectural Considerations
- Parallelism in DSP processing
- Texas Instruments TMS320 Digital Signal Processor Families
- Fixed Point TI DSP Processors: TMS320C1X and TMS320C2X Family
- TMS320C25 –Internal Architecture
- Arithmetic and Logic Unit
- Auxiliary Registers
- Addressing Modes (Immediate
- Direct and Indirect
- Bit-reverse Addressing)
- Basics of TMS320C54x and C55x Families in respect of Architecture improvements and new applications fields
- TMS320C5416 DSP Architecture
- Memory Map, Interrupt System
- Peripheral Devices
- Illustrative Examples for assembly coding
Unit 3 VLIW Architecture
- Current DSP Architectures
- GPUs as an alternative to DSP Processors
- TMS320C6X Family
- Addressing Modes
- Replacement of MAC unit by ILP, Detailed study of ISA, Assembly Language Programming
- Code Composer Studio
- Mixed C and Assembly Language programming
- On-chip peripherals
- Simple applications developments as an embedded environment
Unit 4 Multi-core DSPs
- Introduction to Multi-core computing and applicability for DSP hardware
- Concept of threads
- introduction to P- thread
- mutex and similar concepts
- heterogeneous and homogenous multi-core systems
- Shared Memory parallel programming –OpenMP approach of parallel programming
- PRAGMA directives
- OpenMP Constructs for work sharing like for loop
- TI TMS320C6678 (Eight Core subsystem)
Unit 5 FPGA based DSP Systems
- Limitations of P-DSPs
- Requirements of Signal processing for Cognitive Radio (SDR)
- FPGA based signal processing design-case study of a complete design of DSP processor
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