VLSI Design Verification and Testing
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Follow on Instagram for UpdatesVLSI Design Verification and Testing Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Design Verification and Testing (subject code 3726102) as prescribed for E(AE · Semester 2 divides the course into 6 units, covering 69 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3726102)Unit 1 Verification guidelines
- Verification Process
- Basic Testbench functionality
- directed testing
- Methodology basics
- Constrained-Random stimulus
- Functional coverage
- Testbench components
- Layered testbench
- Building layered testbench
- Simulation environment phases
- Maximum code reuse
- Testbench performance
Unit 2 Data types
- Built-in data types
- Fixed-size arrays
- Dynamic arrays
- Associative arrays
- Linked lists
- Array methods
- Choosing a storage type
- Creating new types with typedef
- Creating user-defined structures
- Type conversion
- Enumerated types
- Constants strings
- Expression width
Unit 3 Procedural statements and routines
- Procedural statements
- functions and void functions
- Routine arguments
- Returning from a routine
- Local data storage
- Time values Connecting the testbench and design: Separating the testbench and design
- Interface constructs
- Stimulus timing
- Interface driving and sampling
- Connecting it all together
- Top-level scope Program – Module interactions
Unit 4 SystemVerilog Assertions
- Basic OOP: Introduction
- think of nouns
- Not verbs
- your first class
- where to define a class
- OOP terminology
- Creating new objects
- Object de-allocation
- Using objects
- Static variables vs
- Global variables
- Class methods
- Defining methods outside of the class
- Scoping rules
- Using one class inside another
- Understanding dynamic objects
- Copying objects
- Public vs
- Straying off course building a testbench
Unit 5 Randomization
- What to randomize
- Randomization in SystemVerilog
- Constraint details solution probabilities
- Controlling multiple constraint blocks
- Valid constraints
- In-line constraints
- The pre_randomize and post_randomize functions
Unit 6 Random number functions, Constraints tips and techniques, Common randomization
- Iterative and array constraints
- Atomic stimulus generation vs
- Scenario generation
- Random control
- Random number generators
- Random device configuration
- Subject Code: 3726102 w.e.f
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