Analog and Digital CMOS VLSI Design

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ANALOG AND DIGITAL 3726101
FREE PDF 3726101
Code: 3726101 Credits: 4 Semester 2 E(AE

Analog and Digital CMOS VLSI Design

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Analog and Digital CMOS VLSI Design Syllabus — Unit-wise Content

The official GTU curriculum for Analog and Digital CMOS VLSI Design (subject code 3726101) as prescribed for E(AE · Semester 2 divides the course into 6 units, covering 61 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.

Download the official syllabus PDF (3726101)

Unit 1 Review

  • Basic MOS structure and its static behavior
  • Quality metrics of a digital design: Cost
  • Power, and Delay
  • Stick diagram and Layout
  • Wire delay models
  • Inverter: Static CMOS inverter
  • Switching threshold and noise margin concepts and their evaluation
  • Dynamic behavior
  • Power consumption

Unit 2 Physical design flow

  • Floor planning
  • Routing, CTS, Power analysis and IR drop estimation-static and dynamic
  • ESD protection-human body model
  • Machine model
  • Combinational logic: Static CMOS design
  • Logic effort
  • Ratioed logic
  • Pass transistor logic
  • Dynamic logic
  • Speed and power dissipation in dynamic logic
  • Cascading dynamic gates
  • CMOS transmission gate logic

Unit 3 Sequential logic

  • Static latches and registers
  • Bi-stability principle
  • MUX based latches
  • Static SR flip-flops
  • Master-slave edge-triggered register
  • Dynamic latches and registers
  • Concept of pipelining
  • Pulse registers
  • Non-bistable sequential circuit
  • Advanced technologies: Giga-scale dilemma
  • Short channel effects
  • Metal Gate Technology
  • TFET etc Analog CMOS Design:

Unit 4 Single Stage Amplifier

  • CS stage with resistance load
  • Divide connected load
  • Current source load
  • Triode load
  • CS stage with source degeneration
  • Source follower
  • Commongate stage
  • Cascade stage
  • Choice of device models
  • Differential Amplifiers: Basic difference pair
  • Common mode response
  • Differential pair with MOS loads
  • Gilbert cell

Unit 5 Passive and active current mirrors

  • Basic current mirrors
  • Cascade mirrors
  • Active current mirrors
  • Frequency response of CS stage: Source follower
  • Common gate stage
  • Cascade stage and difference pair

Unit 6 Operational amplifiers

  • One stage OPAMP
  • Two stage OPAMP
  • Gain boosting
  • Common mode feedback
  • Slew rate
  • Compensation of 2 stage OPAMP
  • Other compensation techniques
  • Subject Code: 3726101 w.e.f

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