SoC Design
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Follow on Instagram for UpdatesSoC Design Syllabus — Unit-wise Content
The official GTU curriculum for SoC Design (subject code 3726104) as prescribed for E(AE · Semester 2 divides the course into 6 units, covering 39 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3726104)Unit 1 ASIC - Overview of ASIC types, design strategies, CISC, RISC and NISC approaches for SOC
- architectural issues and its impact on SoC design methodologies
- Application Specific Instruction Processor (ASIP) concepts
Unit 2 NISC - NISC Control Words methodology, NISC Applications and Advantages, Architecture
- Description Languages (ADL) for design and verification of Application Specific Instruction set Processors (ASIP)
- No-Instruction-Set-computer (NISC)- design flow
- modeling NISC architectures and systems
- use of Generic Netlist Representation - A formal language for specification
- compilation and synthesis of embedded processors
Unit 3 Simulation
- Different simulation modes
- static timing
- gate level
- switch level
- transistor/circuit simulation
- design of verification vectors
- Low power FPGA
- Reconfigurable systems
- SoC related modeling of data path design and control logic
- Minimization of interconnects impact
- clock tree design issues
Unit 4 Low power SoC design / Digital system
- Design synergy
- Low power system perspective- power gating
- clock gating
- adaptive voltage scaling (AVS)
- Static voltage scaling
- Dynamic clock frequency and voltage scaling (DCFS)
- building block optimization
- building block memory
- power down techniques
- power consumption verification
Unit 5 Synthesis
- Role and Concept of graph theory and its relevance to synthesizable constructs
- trails paths
- nodal and admittance graph
- Technology independent and technology dependent approaches for synthesis
- optimization constraints
- Synthesis report analysis Single core and Multi core systems
- dark silicon issues
- HDL coding techniques for minimization of power consumption
- Fault tolerant designs
Unit 6 Case study for overview of cellular phone design with emphasis on area optimization, speed
- improvement and power minimization Note: Students will prepare and present a term paper on relevant identified current topics (in batches of three students per topic) as a part of theory course
- Subject Code: 3726104 w.e.f
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