Digital Techniques
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Follow on Instagram for UpdatesDigital Techniques Syllabus — Unit-wise Content
The official GTU curriculum for Digital Techniques (subject code DI02000181) as prescribed for Nano · Semester 2 divides the course into 5 units, covering 15 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (DI02000181)Unit 1 Number Systems & Codes 08 20
- 1.1 Number Systems 1.1.1 Types of Number System(Binary
- Octal & Hexadecimal) 1.1.2 Base or Radix of Number system 1.1.3 Conversion of Number System from one number system to another number system. 1.2 Binary Arithmetic(Addition
- Multiplication and Division) 1.3 Complements 1.3.1 1’s & 2’s Complements 1.3.2 Subtraction using 1’s & 2’s Complements 1.4 Codes 1.4.1 BCD, Gray Code
Unit 2 Logic Gates & Boolean Algebra 11 25
- 2.1 Two state logical operation 2.1.1 Represent signals in logic 0 and logic 1 in Positive and Negative logic system. 2.2 Tristate logic operation Program Name: Engineering Level: Diploma Branch: Instrumentation & Control / Automation & Robotics Course / Subject Code: DI02000181 Course/Subject Name: Digital Techniques w.e.f. 2024-25 http://syllabus.gtu.ac.in/ Page no. 3 of 10 2.3 Logic Gates: 2.3.1 Basic Gates: AND, OR, NOT Gate Universal Gates: NAND and NOR Gate Special purpose gates: EX-OR and EX-NOR Gate 2.3.2 Symbol
- Logical Expression
- Truth Table, and Electrical equivalent circuit of each gate 2.3.3 Implementation of AND, OR and NOT gate using Universal gates. 2.4 Boolean Algebra: 2.4.1 Laws
- Theorems and Postulates of Boolean Algebra 2.4.2 State and verification of De Morgan’s First and Second theorem. 2.4.3 Listing of Boolean expressions for Properties of Boolean Algebra. 2.4.4 Duality Theorems 2.4.5 Simplification of given expression using Boolean Algebra 2.4.6 Development of Logic circuit using the given Boolean Expression
Unit 3 Digital Logic Simplification 08 15 3.1 Standard Boolean representation
- 3.1.1 Sum of Product (SOP) and Product of Sum (POS) 3.1.2 Min-Term & Max-Term 3.1.3 Conversion between SOP & POS form. 3.1.4 Realization using NAND/NOR Gates 3.2 K-map reduction technique for the Boolean expression: 3.2.1 Minimization of Boolean expressions (upto 4 variables) using SOP and POS form 3.2.2 Don't care condition in K-map
Unit 4 Combinational Logic Circuits 08 20
- 4.1 Arithmetic Circuits 4.1.1 Half Adder
- Full Adder
- Half Subtractor
- Full Subtractor
- Block diagram of parallel adder using full adder block (up to 4 - bit) 4.2 Decoder: 2 to 4 & 3 to 8 Program Name: Engineering Level: Diploma Branch: Instrumentation & Control / Automation & Robotics Course / Subject Code: DI02000181 Course/Subject Name: Digital Techniques w.e.f. 2024-25 http://syllabus.gtu.ac.in/ Page no. 4 of 10 4.3 Encoder: 4 to 2 & 8 to 3 4.4 Multiplexer: 4 to 1 4.5 Demultiplexer: 1 to 4 4.6 Code Converter: Gray to Binary and Binary to Gray (up to 4 bits)
Unit 5 Sequential Logic Circuit 10 20
- 5.1 Sequential Circuit: Introduction 5.1.1 Terms related to sequential Circuit: Digital Clock & Duty cycle 5.1.2 Block Diagram of sequential circuit 5.1.3 Comparison of Combinational & Sequential Logic Circuit 5.1.4 Classification of Sequential Circuits 5.1.5 Flips- Flops and Latch 5.1.6 RS-Latch using NAND and NOR 5.1.7 Triggering methods-Edge trigger and Level Trigger 5.2 Flip-Flops: S-R
- T and D 5.2.1 Truth table and logic circuits of each flip-flop 5.3 Counters 5.3.1 Asynchronous up and down counter (up to 4 bit) 5.3.2 Synchronous up and down counter (up to 4 bit)
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