Digital Logic Design
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Follow on Instagram for UpdatesDigital Logic Design Syllabus — Unit-wise Content
The official GTU curriculum for Digital Logic Design (subject code DI03000111) as prescribed for IC · Semester 3 divides the course into 5 units, covering 26 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (DI03000111)Unit 1 Number systems and codes
- 1.1. Introduction to various number systems: Binary, Octal, Decimal, Hexadecimal.
- 1.2. Conversion from one number system to another and vice-versa.
- 1.3. Binary arithmetic operations:
- 1.3.1. addition, subtraction, multiplication and division
- 1.3.2. 1’s and 2’s Complement of binary number & subtraction using 1’s and 2’s complement method.
Unit 2 Boolean algebra and logic gates
- 2.1. Digital Logic Gates: Symbol, operation and truth-table of AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR gates.
- 2.2. Basic theorems and properties of Boolean algebra.
- 2.3. Implementations of Boolean function using AND-OR -Invert logic gates
- 2.4. Universal Gates: NAND & NOR
- 2.5. Algebraic simplification of Boolean expression using Boolean algebra
- 2.6. Sum of Product (SOP) definition and Simplification of Boolean function using Karnaugh map (K-map) up to 4-variables
- 2.7. Don't care condition in K-map. GUJARAT TECHNOLOGICAL UNIVERSITY Program Name: Engineering Level: Diploma Branch: Information & Communication Technology / Electronics & Communication Engineering Course / Subject Code : DI03000111 Course / Subject Name :Digital Logic Design w.e.f. 2025-26 http://syllabus.gtu.ac.in/ Page 4 of 10
Unit 3 Combinational logic circuits
- 3.1. Arithmetic Circuits: Design Half adder, full adder, half subtractor, full subtractor; Block diagram of parallel adder using half and full adder block (up to 4 - bit)
- 3.2. Encoder (4:2, 8:3); Decoder (2:4, 3:8)
- 3.3. Multiplexers (2:1, 4:1, 8:1) De-multiplexers (1:2, 1:4, 1:8)
- 3.4. Binary to Gray and Gray to binary code converters up to 4 bits.
Unit 4 Sequential logic circuits
- 4.1. Flip-flops: SR, D, JK, T, Master Slave JK;
- 4.2. Triggering methods
- 4.3. Shift Registers: Classification of Shift Registers- (i)Serial in serial-out, (ii) serial-in parallel-out, (iii) parallel-in serial- out and (iv) parallel-in parallel out.
- 4.3. Counters: Ring Counter, Johnson Counter, 4 bit Asynchronous (Ripple) Counter, 4 bit Synchronous up/down Counter, BCD/Decade counter.
Unit 5 Introduction to Memories and logic families
- 5.1. Introduction and Types of Memory:
- 5.1.1. RAM (SRAM, DRAM)
- 5.1.2. ROM (PROM, EPROM, EEPROM)
- 5.2. Overview of different logic family Definitions: Fan in, Fan out, Noise margin, Propagation delay, Power GUJARAT TECHNOLOGICAL UNIVERSITY Program Name: Engineering Level: Diploma Branch: Information & Communication Technology / Electronics & Communication Engineering Course / Subject Code : DI03000111 Course / Subject Name :Digital Logic Design w.e.f. 2025-26 http://syllabus.gtu.ac.in/ Page 5 of 10 dissipation, Figure of merit.
- 5.3. Comparison of different logic families (TTL, CMOS, ECL)
- 5.4. E-waste Management of Digital ICs/Chips
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