VLSI Design Verification
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Follow on Instagram for UpdatesVLSI Design Verification Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Design Verification (subject code ME01000411) as prescribed for EAC( · Semester 1 divides the course into 6 units, covering 39 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME01000411)Unit 1 The Verification Plan
- The Role of the Verification Plan
- Levels of Verification
- Verification Strategies
- From Specification to Features
- From Features to test cases
- From Test cases to Test benches
Unit 2 Verification Tools
- Linting Tools
- Third-Party Models
- Waveform Viewers
- Code Coverage
- Verification Languages
- Revision Control
- Issue Tracking, and Metrics
- WEF Academic Year : 2024 – 25 Semester : 1st Semester Category of the Course : PEC Program Name: Master of Engineering Level: PG Branch: Electronics & Communication (VLSI System Design) Course / Subject Code : ME01000411 Course / Subject Name : VLSI Design Verification
Unit 3 Functional Verification Methods and Tools
- Test bench architecture
- Simulation tools
- Functional and code coverage 6 15
Unit 4 Formal Verification Methods
- Binary Decision Diagram
- Equivalence Checking
- Assertion based verification
Unit 5 Introduction to System Verilog
- System Verilog modeling concepts
- Data types
- syntax rules
- Procedural blocks and assignments
- Programming statements
- Operators and operation rules
- Compound data types and packages
- System Verilog interface ports
- Verification constructs and test bench interfaces
- Verification timing using clocking blocks
- Object Oriented test bench
- Dynamic arrays and scoreboards
- Constrained random stimulus generation
- Functional coverage
- Synchronization (events
- Assertions overview
Unit 6 Universal Verification Methodology (UVM)
- Overview of UVM, Object Oriented Programming
- UVM library Basics
- Interface Universal Verification Component 12 20
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