Fundamentals of VLSI CAD

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KHUDKIBOOK
FUNDAMENTALS OF VLSI 3712609
FREE PDF 3712609
Code: 3712609 Credits: 4 Semester 1 EAC(

Fundamentals of VLSI CAD

Get the full GTU study material, English & Gujarati textbook PDFs, syllabus curriculum, and solved previous year question papers.

Fundamentals of VLSI CAD Syllabus — Unit-wise Content

The official GTU curriculum for Fundamentals of VLSI CAD (subject code 3712609) as prescribed for EAC( · Semester 1 divides the course into 7 units, covering 34 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.

Download the official syllabus PDF (3712609)

Unit 1 Introduction

4 lecture hours

  • Introduction to VLSI Design methodologies and abstraction levels
  • The VLSI Design Problem
  • The design domains
  • design actions
  • design methods and technologies

Unit 2 Algorithmic Graph Theory

5 lecture hours

  • Terminology of graph
  • Data Structures for the Representation of Graphs
  • Computational Complexity
  • Examples of Graph Algorithms- Depth-first Search
  • Breadth-first Search etc, Time and space complexity of algorithms

Unit 3 Tractable and Intractable Problems

5 lecture hours

  • Combinatorial Optimization Problems
  • Decision Problems
  • Complexity Classes
  • NP-completeness and NP-hardness

Unit 4 General-purpose Methods for Combinatorial Optimization

6 lecture hours

  • The Unit-size Placement Problem
  • Backtracking and Branch-and-bound
  • Dynamic Programming
  • Integer Linear Programming
  • Local Search
  • Simulated Annealing
  • Tabu Search
  • Genetic Algorithms

Unit 5 Logic Synthesis and Verification

6 lecture hours

  • Introduction to Combinational Logic Synthesis
  • Binary-decision Diagrams
  • Two-level Logic Synthesis

Unit 6 High-level Synthesis

12 lecture hours

  • Hardware Models for High-level Synthesis
  • Internal Representation of the Input Algorithm
  • Assignment and Scheduling
  • Some Scheduling Algorithms
  • Some Aspects of the Assignment Problem
  • High-level Transformations

Unit 7 Simulation

42 lecture hours

  • General Remarks on VLSI Simulation
  • Gate-level Modeling and 4 10 Simulation
  • Switch-level Modeling and Simulation

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