VLSI Test Principals and Architectures
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Follow on Instagram for UpdatesVLSI Test Principals and Architectures Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Test Principals and Architectures (subject code 2732605) as prescribed for EAC( · Semester 3 divides the course into 5 units, covering 33 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (2732605)Unit 1 Introduction
- Importance of Testing
- Testing during VLSI Lifecycle
- Challenges in VLSI Testing
- Levels of Abstraction in VLSI Testing
- Historical Review of VLSI Test Technology
Unit 2 Design and Testability
- Testability Analysis
- Design for Testability Basics
- Scan Cell Designs
- Scan Architectures
- Scan Design Rules
- Scan Design Flow
- Special purpose Scan Designs
- RTL Design for Testability
Unit 3 Logic and Fault Simulation
- Simulation Models
- Logic Simulation
- Fault Simulation
Unit 4 Test Generation
- Random Test Generation
- Theoretical Background: Boolean Difference
- designing a Stuck-At ATPG for Combinational Circuits
- Designing a Sequential ATPG
- Untestable Fault Identification
- Designing a Simulation-Based ATPG
- Advanced Simulation-Based ATPG
- Hybrid Deterministic and Simulation-Based ATPG
- ATPG for Non-Stuck-At Faults
- Other Topics in test Generation
Unit 5 Logic Built-In Self-Test
- BIST Design Rule
- Test Pattern Generation
- Output Response Analysis
- Logic BIST Architectures
- Fault Coverage Enhancement
- BIST Timing /Control
- Design Practice
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