VLSI Design Verification Techniques
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Follow on Instagram for UpdatesVLSI Design Verification Techniques Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Design Verification Techniques (subject code ME02004031) as prescribed for EACE · Semester 2 divides the course into 6 units, covering 29 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (ME02004031)Unit 1 The Verification Plan The Role of the Verification Plan, Levels of
- Verification Strategies
- From Specification to Features
- From Features to test cases
- From Test cases to Test benches
Unit 2 Verification Tools Linting Tools, Simulators, Third-Party Models,
- Waveform Viewers
- Code Coverage
- Verification Languages
- Revision Control
- Issue Tracking, and Metrics
Unit 3 Functional Verification Methods and Tools Concept, Test bench
- Simulation tools
- Functional and code coverage. 8 15
Unit 4 Formal Verification Methods Binary Decision Diagram, Equivalence
- Assertion based verification
Unit 5 Introduction to System Verilog System Verilog modeling concepts, Data
- syntax rules
- Procedural blocks and assignments
- Programming statements
- Operators and operation rules
- Compound data types and packages
- System Verilog interface ports
- Verification constructs and testbench interfaces
- Verification timing using clocking blocks
- Object Oriented testbench
- Dynamic arrays and scoreboards
- Constrained Subject Code : ME02004031 Subject Name : VLSI Design Verification Techniques random stimulus generation
- Functional coverage
- Synchronization (events
- Assertions overview
Unit 6 Universal Verification Methodology (UVM) Introduction, Overview of
- UVM, Object Oriented Programming
- UVM library Basics
- Interface Universal Verification Component
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