Unit 1 Introduction

• ASIC Design flow
• Design Methodologies
• Hardware modelling issues
• Overview of FPGA and CPLD technology. 2 5

Unit 2 Hardware Description Language

6 lecture hours

• Elements of VHDL
• configuration declaration
• data types and operators
• Assignment statement
• Objects in VHDL – signals
• Attributes of objects. w. e. f
• Academic Year: 2024-25 Semester: 1st Semester Category of the Course: PCC Program Name: Master of Engineering Level: PG Branch: Electronics & Communication Engineering Course / Subject Code : ME01004021 Course / Subject Name : ASIC Design

Unit 3 Behavioural modelling

7 lecture hours

• Process statement
• Signal and variable assignment
• Wait statement
• if statement
• Case statement
• exit, and next statement
• Assertion and report statement
• Multiple process
• Postponed process
• Subprograms – procedures and functions
• Subprogram overloading and operator Overloading
• RTL description

Unit 4 Dataflow modelling

7 lecture hours

• Concurrent signal assignment
• sequential signal assignment
• delta delay
• multiple drivers
• conditional signal assignment using when … else
• selected signal assignment using with select
• block statement
• concurrent Assertion signal

Unit 5 Structural modelling

4 lecture hours

• Component declaration
• generics and component instantiation
• Example of making hierarchical circuit
• Generate statement
• mixed Modelling style

Unit 6 Finite State Machine (FSM)

5 lecture hours

• Stat diagrams and state tables
• Moore and Mealy finite state machine
• encoding style
• FSM issues
• Timing issues
• resource sharing
• MTBF Analysis
• setup/hold time of various types of flip-flops
• synchronization between multiple clock Domains
• reset recovery

Unit 7 Configuration and packages

2 lecture hours

• Configuration specification and declaration
• conversion functions
• direct Instantiation
• incremental binding
• Package declaration
• package body
• design file

Unit 8 Test Benches and library

2 lecture hours

• File I/O operations
• Test bench architecture
• test bench examples
• library Declaration and user defined library
• Program Name: Master of Engineering Level: PG Branch: Electronics & Communication Engineering Course / Subject Code : ME01004021 Course / Subject Name : ASIC Design

Unit 9 Programmable Logic Design

10 lecture hours

• Basics of Programmable logic devices - PROM, PAL, PLA, etc.
• CPLD architecture and its building blocks
• FPGA architectures and its building blocks
• Carry chains in FPGA
• Dedicated multipliers and memory in FPGA
• RTL synthesis test methodology
• Design synthesis
• Technology mapping for FPGAs: SRAM
• EPROM programming techniques
• Design implementation using CPLD and FPGA
• Floor Planning
• Placement and routing