Unit 1 Introduction to VLSI Design and Verilog

3 lecture hours

• Conventional approach to digital design
• VLSI design
• ASIC design flow
• Role of HDL, Verilog as an HDL, Levels of design description
• Simulation and synthesis
• Functional verification
• System tasks
• Programming language interface
• Simulation and synthesis tools
• Test benches

Unit 2 Language Constructs and Conventions in Verilog

3 lecture hours

• White space characters
• Logic values
• Data types
• Scalars and vectors
• System tasks

Unit 3 Architecture of FPGA

4 lecture hours

• Generic FPGA architecture
• Architectural overview
• Program design flow
• Device programming
• Design implementation using FPGA
• Floor planning and architecture design: floor planning methods
• off-chip connections
• High –level synthesis
• Architecture testing

Unit 4 Gate Level Modelling

4 lecture hours

• Basic gate primitives
• Module structure
• Tri state gates
• Array of instances of primitives
• Design of flip-flops with gate primitives
• Strengths and contention resolution
• Net types
• Design of basic circuits

Unit 5 Modelling at Data Flow Level

6 lecture hours

• Continuous assignment structures
• Delays and continuous assignments
• Assignment to vectors

Unit 6 Behavioural Modeling

6 lecture hours

• Operations and assignments
• Functional Bifurcation
• always and wait constructs
• Assignments with delays
• Multiple always blocks
• Design at behaviour level
• Blocking and non-blocking assignments
• Case statement
• Simulation flow
• If and if-else
• assign-de assign
• disable and force-release constructs, For, while and forever loops
• Parallel blocks

Unit 7 User Defined Primitives and FSM

• User-defined primitives (UDP)
• Mealy and Moore finite state machine. 4 9%

Unit 8 Architecting Speed, Area and Power

• 10 22% Program Name: Master of Engineering Level: PG Branch: Applied Instrumentation Subject Code : ME02067091 Subject Name : Advance VLSI Design High throughput
• Low latency
• Rolling Up the pipeline
• Resource sharing
• Impact of reset on area
• Clock control
• Input control
• Reducing the voltage supply
• Dual edge triggered flip-flops

Unit 9 Clock Domains

• Crossing clock domains
• Gated clocks in ASIC prototypes. 5 11%