VLSI Design
Get the full GTU study material, English & Gujarati textbook PDFs, syllabus curriculum, and solved previous year question papers.
English Book & Chapters
English Book Coming Soon
We are working hard to add this material. Stay tuned for updates!
Follow on Instagram for UpdatesGTU Previous Year Papers
Papers Coming Soon
We are working hard to add this material. Stay tuned for updates!
Follow on Instagram for UpdatesVLSI Design Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Design (subject code BE05000371) as prescribed for EC-CS · Semester 5 divides the course into 8 units, covering 42 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (BE05000371)Unit 1 Introduction
- Overview of VLSI design methodology
- VLSI design flow
- Design hierarchy
- Concept of regularity
- Modularity, and Locality
- VLSI design style
- Design quality
- package technology
- introduction to FPGA and CPLD
- computer aided design technology
- Teaching/Learning Scheme in hrs/semester Total Credits Assessment Pattern and Marks Total Marks L T P PBL* TH TH/30 Theory Practical ESE (E) PA (M) PA (I) PBL(I) ESE (V) 45 0 30 15 90 3 70 30 20 30 50 200 Program Name: Bachelor of Engineering Level: UG Branch: Electronics and Communication Subject Code: BE05000371 Subject Name: VLSI Design
Unit 2 Fabrication of MOSFET
- Fabrication Process flow: Basic steps
- C-MOS n- WellProcess
- Layout Design rules
- full custom mask layout design
Unit 3 MOS Transistor
- The Metal Oxide Semiconductor (MOS) structure
- The MOS System underexternal bias
- Structure and Operation of MOS transistor
- MOSFET Current-Voltage characteristics
- MOSFET scaling and small-geometry effects
Unit 4 MOS Inverters - Static Characteristics
- Resistive load Inverter
- Inverter with n-type MOSFET load(Enhancement and Depletion type MOSFET load)
- CMOS Inverter
Unit 5 MOS Inverters Switching characteristics and Interconnect Effects
- Delay-time definitions
- Calculation of Delay times
- Inverter designwith delay constraints
- Estimation of Interconnect Parasitic
- Calculation ofinterconnect delay
- Switching Power Dissipation of CMOS Inverters
Unit 6 Combinational MOS Logic Circuits
- MOS logic circuits with Depletion nMOS Loads
- CMOS logiccircuits
- Complex logic circuits
- CMOSTransmission Gates (TGs)
Unit 7 Sequential MOS Logic Circuits
- Behavior of Bistable elements
- The SR latch circuit
- Clockedlatch and Flip-flop circuit
- CMOS D-latch and Edge-triggered flip- flop
Unit 8 Dynamic Logic Circuits
- Basic Principles of pass transistor circuits
- Voltage Bootstrapping
- Synchronous Dynamic Circuit Techniques
- CMOS DynamicCircuit Techniques
- High-performance Dynamic CMOS circuits
Study on Android App:
