VLSI System
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Follow on Instagram for UpdatesVLSI System Syllabus — Unit-wise Content
The official GTU curriculum for VLSI System (subject code DI05000021) as prescribed for Marine · Semester 5 divides the course into 5 units, covering 27 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (DI05000021)Unit 1 MOS TRANSISTOR
- 1.1 Explain Energy band diagram and structure of MOS 1.2 MOS system under external bias 1.3 Symbols for different MOSFET 1.4 Structure and operation of MOSFET 1.5 Channel formation 1.6 Gradual channel Approximation 1.7 MOSFET Current-Voltage characteristics 1.8 Needs of scaling 1.9 Full-Voltage Scaling
- Constant-Voltage Scaling. 1.10 Effect of Scaling 1.11Dual Gate MOSFET: Concept
- Advantages and Limitations 1.12Silicon on Insulator(SOI): Concept
- Advantages and Limitations 1.13 High-K metal gate MOSFET: Concept
- Advantages and Limitations 1.14 FIN-FET: Concept
- Advantages and Limitations 1.15 Gate All Around(GAA) FET: Concept
- Advantages and Limitations
Unit 2 MOS INVERTERS
- 2.1 Concept and working of Ideal Inverter 2.2 Noise Margin and Noise Immunity 2.3 Voltage Transfer Characteristic of Ideal Inverter 2.4 Working and VTC of Resistive Load Inverter (without derivation) 2.5 Working and VTC of Depletion load Inverter (without derivation) 2.6 Working and VTC of CMOS inverter (without derivation) Program Name: Diploma Engineering Level: Diploma Branch: Electronics & Communication Engineering / Information & Communication Technology Subject Code : DI05000021 Subject Name : VLSI System
Unit 3 MOS CIRCUIT
- 3.1 Two Input NAND and NOR Gate with depletion NMOS load 3.2 Combinational MOS logic circuits with Depletion nMOS Loads 3.3 Two input NAND and NOR Gate using CMOS logic. 3.4 AOI and OAI complex Logic circuits using CMOS 3.5 Simple XOR/XNOR function using CMOS logic 3.6 Complex logic circuits using CMOS logic 3.7 NOR gate based SR latch using CMOS logic 3.8 NAND gate based SR latch using CMOS logic 3.9 Clocked NOR based SR latch using CMOS logic 3.10Clocked NOR based JK latch using CMOS logic 3.11Clocked NOR based D latch using CMOS logic
Unit 4 FABRICATION OF MOSFET
- 4.1 VLSI design flow representation using Y chart 4.2 Define terms: Hierarchy
- Locality 4.3 FPGA: Architecture
- Application and Limitations 4.4 CMOS Fabrication using CMOS n- Well Process 4.5 Diffusion 4.6 Ion implantation 4.7 Oxidation 4.8 Photolithography 4.9 Etching 4.10Deposition Program Name: Diploma Engineering Level: Diploma Branch: Electronics & Communication Engineering / Information & Communication Technology Subject Code : DI05000021 Subject Name : VLSI System
Unit 5 INTRODUCTION TO VERILOG
- 5.1 Basic Features of Verilog HDL 5.2 Module Definition 5.3 Data types: wire, reg, constants 5.4 AND, OR, NOT, XOR, XNOR
- NAND and NOR gate implementation using dataflow
- structural and behavioural modelling in Verilog 5.5 Verilog code for Adder and Subtractor circuits : Half Adder
- Full Adder
- Half Subtractor
- Full Subtractor
- Full Adder using Half Adder
- 4 bit full adder 5.6 Verilog Programs related to Combinational circuits: Multiplexer and Demultiplexer
- Decoder and Encoder
- Parity Generator and Parity Checker 5.7 Test bench: Structure
- instantiation of design module in testbench
- stimulus generation. 5.8 Use of initial
- always and forever blocks in testbench for applying inputs. 5.9 Simple testbench example for Basic gates. 5.10 Verilog programs related to basic Sequential circuits : SR latch
- Parallel Input Parallel Output Shift Register
- 4- Bit Binary Up Counter/ Down counter
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