VLSI Technology
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VLSI Technology Syllabus — Unit-wise Content
The official GTU curriculum for VLSI Technology (subject code 4353206) as prescribed for ICT · Semester 5 divides the course into 4 units, covering 23 listed topics. This curriculum applies from the 7/1/2024 12:00:00 AM intake. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (4353206)Unit 1 MOS Transistor 2a Explain MOSFET structure and its working under different bias conditions. 1.6 Explain Energy band Diagram and Structure...
- 1.7. The MOS System under External Bias 2b Explain Operation of MOS Transistor (MOSFET) and voltage- current characteristics
- 2.1. Channel formation
- 2.2. Symbols for different MOSFET
- 2.3. MOSFET Current- Voltage characteristics
- 2.4. Gradual channel Approximation 2c Explain MOSFET Scaling 2.5 Needs of scaling
- 2.6. Full-Voltage Scaling, Constant-Voltage Scaling.
- 2.7. Effect of Scaling
Unit 2 MOS Inverters 3a Describe Basics of MOSFET inverter 3.1 Concept and working of Ideal Inverter
- 3.2. Noise Margin 3.3Voltage Transfer Characteristics 3b Describe Resistive load Inverter 3.4 Working and VTC without derivation 3c Differentiate Inverter with n-type MOSFET load (Enhancement & Depletion type MOSFET load),
- 3.5. Working and VTC without derivation for Enhancement & Depletion type MOSFET load 3d Explain CMOS Inverter and its characteristics 3.6 Working and VTC without derivation for CMOS inverter
Unit 3 MOS Circuits 4a Explain two input NAND and NOR Gate with depletion NMOS load.
- 4.1. MOS logic circuits with Depletion nMOS Loads 4b Explain Two input NAND and NOR Gate using CMOS logic.
- 4.2. CMOS logic circuits ,Stick Diagram, Euler path Approach 4c Differentiate AOI and OAI Logic. Design simple XOR function
- 4.3. Complex logic circuits 4d Describe the working of SR latch circuit. Distinguish Clocked latch and Flip-Flop circuit
- 4.4. The SR latch circuit,
- 4.5. Clocked latch and Flip- flop circuit
- 4.6. CMOS D-latch and Edge-triggered flip- flop
Unit 4 Verilog Programmin g 5a Describe Verilog: HDL fundamentals, simulation, coding style and test-bench design
- 7.1. Module definition
- 7.2. RTL coding style: Gate level, Data flow, Behavioral, Mixed approach
- 7.3. Stimulus generation 5b Develop Verilog Programs related to basic logic gates
- 5.4. Basic Logic gate implementation in Verilog 5c Develop Verilog Programs related to Fundamental Arithmetic operations.
- 5.5. Verilog code for adder and subtractor circuits 5d Develop Verilog Programs related to Combinational circuits.
- 5.6. Combinational circuits: Multiplexer , Demultiplexer, Decoder and Encoder, Parity Generator and parity checker. 5e Develop Verilog Programs related to Sequential circuits.
- 5.7. Basic Sequential circuits : SR latch, D F/F, T F/F, JK F/F
- 5.8. Parallel input Parallel output Shift Register, Up Counter, Down Counter
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