VLSI
Get the full GTU study material for this subject: official syllabus, textbook links (Gujarati-medium books included where available), and previous year question papers.
English Book & Chapters
English Book Coming Soon
We are working hard to add this material. Stay tuned for updates!
Follow on Instagram for UpdatesGTU Previous Year Papers
VLSI Syllabus — Unit-wise Content
The official GTU curriculum for VLSI (subject code 4361102) as prescribed for EC · Semester 6 divides the course into 4 units, covering 15 listed topics. This curriculum applies from the Jan-2024 intake. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (4361102)Unit 1 MOS Inverters 2a Explain the working of MOS Inverter 2.1 MOS Inverter : concept and working 2b Explain operation of resistive load invert...
- 2.2. Resistive load Inverter 2c Describe inverter circuit with saturated and Linear Enhancement type load
- 2.3. Inverter with n-type MOSFET Load, Enhancement load NMOS 2d Explain Depletion type load and compare enhancement load NMOS with Depletion Load NMOS.
- 2.4. Depletion Load NMOS 2e Explain CMOS Inverter with different Operating Modes of nMOS and pMOS transistor.
- 2.5. CMOS Inverter: Circuit operation and description
Unit 2 MOS Circuits 3a Explain two input NAND and NOR Gate with depletion NMOS load
- 3.1. Combinational Logic Circuits. MOS 3b Explain Two input NAND and NOR Gate using CMOS logic.
- 3.2. CMOS logic circuits 3c Differentiate AOI and OAI Logic 3.3 Complex logic circuit 3d Design simple XOR function. 3e Describe the working of SR latch circuit. 3.4 Sequential MOS circuit 3f Distinguish Clocked latch and Flip-Flop circuit.
Unit 3 Fabrication of MOSFET 4a Overview of VLSI design methodology and VLSI design flow
- 4.1. VLSI design flow, Y chart 4b Design hierarchy, Concept Modularity, and Locality of regularity, 4.2 Define terms: hierarchy, regularity, modularity, locality 4c Fabrication Process flow: Basic steps, CMOS n- Well Process
- 4.3. Lithography, Etching, Deposition, Oxidation, Ion implantation, Diffusion
Unit 4 Introduction to VERILOG 5a Verilog: HDL fundamentals, simulation, and test- bench design
- 5.1. Module definition and Stimulus generation 5b Develop Verilog Programs related to basic logic gates
- 5.2. Logic gate implementation in Verilog 5c Develop Verilog Programs related to Fundamental Arithmetic operations.
- 5.3. Verilog for and subtractor circuits adder 5d Develop Verilog Programs related to Combinational circuits.
- 5.4. Combinational circuits : Multiplexer , Demultiplexer, Decoder and Encoder
- 5.5. Parity Generator and parity checker. 5e Develop Verilog Programs related to Sequential circuits.
- 5.6. Basic Sequential circuits : SR latch, D F/F, T F/F, JK F/F
- 5.7. Parallel input Parallel output Shift Register, Up Counter, Down Counter
Study on Android App:
