Computer Organization and Architecture
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Computer Organization and Architecture Syllabus — Unit-wise Content
The official GTU curriculum for Computer Organization and Architecture (subject code 4350701) as prescribed for Chem. Green · Semester 5 divides the course into 4 units, covering 45 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (4350701)Unit 1 Basics of Computer Organization and Processor Evolution
- 1.1. Classify Evolution of intel Processors
- 1.2. Prepare chart of Basic CPU Structure & Registers
- 1.3. Differentiate Bus Organization
- 1.1.1. Observe the characteristic of Intelprocessor from 4 bit (4004) to i7
- 1.2.1. Basic CPU Structure CU, ALU and MU
- 1.2.2. Various Registers used in CPU & its applications AC, DR, AR, PC, MAR, MBR, IR
- 1.3.1. Types of Buses used in CPU Common / Shared Bus v/s Dedicated Bus Serial Bus v/s Parallel Bus Unit – II 8085 Microprocessor
- 2.1. Make a chart of 8085 Microprocessor architecture and describe it.
- 2.2. Interpret 8085 Instruction Execution
- 2.1.1. 8085 Pin Diagram & Pin Functions
- 2.1.2. 8085 Microprocessor Architecture
- 2.1.3. 8085 General Purpose Registers
- 2.1.4. 8085 Flag Register
- 2.2.1. 8085 Instruction Execution ● Fetch ● Decode ● Execute operations Computer Organization & Architecture Course Code: 4350701
Unit 2 8085 Assembly Language Programmin g
- 3.1. Describe Machine Language Instruction Format & Addressing Modes
- 3.2. Develop programs using
- 8085. Instruction Set
- 3.3. Classify various Interrupts of8085
- 3.1.1. Instruction format opcode & Operands
- 3.1.2. Machine Language Instruction Format: 1-Byte, 2-Byte & 3-Byte
- 3.1.3. 8085 Addressing Modes
- 3.2.1. Data transfer Instructions
- 3.2.2. Arithmetical Instructions
- 3.2.3. Logical Instructions
- 3.2.4. Branching & Looping Instructions
- 3.2.5. Stack Instructions
- 3.2.6. I/O and Machine ControlInstructions
- 3.3.1. Classification of 8085 Interrupts and its priorities
- 3.3.2. 8085 Vectored interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and RST Instruction
- 3.3.3. 8085 Non-Vectored Interrupts: INTR Computer Organization & Architecture Course Code: 4350701
Unit 3 Memory Organizati on
- 4.1. Classify Memory Types and Memory Hierarchy
- 4.2. Differentiate types of Main memory, Auxiliary memory, Cache and Virtual Memory
- 4.1.1. Memory classifications
- 4.1.2. Memory Hierarchy
- 4.2.1. Various types of Main memories ● RAM ● ROM ● PROM ● EPROM ● EEPROM ● Associative Memory
- 4.2.2. Various types of Auxiliary memories ● Magnetic tape ● Floppy disk ● Hard Disks ● Flash Memory
- 4.2.3. Cache Memory
- 4.2.4. Virtual Memory
Unit 4 Input- Output Organizati on
- 5.1. Explain I/O interface
- 5.2. Differentiate various Modes ofData Transfer with I/O
- 5.3. Describe Input-Output Processor (IOP)
- 5.4. Describe CPU- IOP communication
- 5.1.1. Input-Output Interface
- 5.1.2. Programmed I/O and Interrupt initiated I/O
- 5.1.3. CPU-IOP communication Note: The UOs need to be formulated at the ‘Application Level’ and above of Revised Bloom’s Taxonomy’ to accelerate the attainment of the COs and the competency.
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