Computer Organization And Architecture
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Computer Organization And Architecture Syllabus — Unit-wise Content
The official GTU curriculum for Computer Organization And Architecture (subject code 3340705) as prescribed for Auto · Semester 4 divides the course into 5 units, covering 30 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3340705)Unit 1 Computer Architecture & Register- Transfer and Micro- operations
- 1.1. Overview of computers and basics of Digital Electronics-Flip Flops, Registers, Shift registers
- 1.3. Register Transfer
- 1.4. Bus Transfer and Memory Transfer
- 1.8. Arithmetic Logic Shift Unit
Unit 2 Basic Computer Organization
- 2.1. Instruction Codes
- 2.2. Computer Registers AC or Accumulator, Data Register or DR, the AR or Address Register, program counter (PC), Memory Data Register (MDR), Index register, Memory Buffer Register.
- 2.3. Computer Instructions
- 2.4. Timing and Control
- 2.5. Instruction Cycle
- 2.6. Memory Reference Instructions
- 2.8. Complete Computer Description
Unit 3 Central processor organization& Pipeline processing
- 3.1. General Register Organization
- 3.2. Stack Organization
- 3.3. Instruction Formats
- 3.5. Data Transfer and manipulation:
- 3.6. Program Control
- 3.8. CISC Characteristics
- 3.9. RISC Characteristics
- 3.10. Parallel Processing
Unit 4 Memory Organization
- 4.1. Memory classifications
- 4.3. Memory Hierarchy
- 4.4. Main Memory and
- 4.5. Auxiliary Memory
- 4.7. Cache Memory
- 4.8. Virtual memory
Unit 5 Input/output Organization
- 5.2. Asynchronous Data Transfer
- 5.3. Strobe Control
- 5.5. Asynchronous Serial Transfer
- 5.6. Modes of Data Transfer
- 5.7. Input-Output Processor (IOP) Computer Organization and Architecture Course Code: 3340705 GTU/ NITTTR Bhopal/12 -13 Gujarat State
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