High Performance Computing
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Follow on Instagram for UpdatesHigh Performance Computing Syllabus — Unit-wise Content
The official GTU curriculum for High Performance Computing (subject code 1716205) as prescribed for IOT · Semester 1 divides the course into 5 units, covering 50 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (1716205)Unit 1 Graphics Processing Units
- Introduction to Heterogeneous Parallel Computing
- GPU architecture
- Thread hierarchy
- GPU Memory Hierarchy
Unit 2 GPGPU Programming
- Vector Addition
- Matrix Multiplication algorithms. 1D, 2D, and 3D Stencil Operations
- Image Processing algorithms – Image Blur
- Reduction Techniques. 06 15 3 UNIT 3: Many Integrated Cores Architectures: 08 20 Wef-AY-2021-22 Introduction to Many Integrated Cores
- MIC, Xeon Phi architecture
- Thread hierarchy
- Memory Hierarchy
- Memory Bandwidth and performance considerations
Unit 3 Xeon Phi Programming
- Vector Addition
- Matrix Multiplication algorithms. 1D, 2D, and 3D Stencil Operations
- Image Processing algorithms – Image Blur
- Reduction techniques
Unit 4 Shared Memory Parallel Programming
- Symmetric and Distributed architectures
- OpenMP Introduction
- Thread creation
- Parallel regions
Unit 5 Message Passing Interface
- MPI Introduction
- Collective communication
- Data grouping for communication. 06 15 Reference Book: 1
- Wen-Mei W Hwu, David B Kirk
- Programming Massively Parallel Processors A Hands-on Approach
- Morgann Kaufmann
- Rezaur Rahman
- Intel Xeon Phi Coprocessor Architecture and Tools
- Apress Open
- Barbara Chapman
- Gabriele Jost
- Ruud van der Pas, Using OpenMP
- MIT Press
- Using MPI, Using MPI, 2014. 5
- D Patterson and J Hennessy
- Computer Organization and Design - The Hardware/Software Interface
- MIPS Edition. 5e
- Computer Organization and Embedded Systems. 6e
- McGraw Hill
- Computer Architecture and Organization, 3e, McGraw Hill
- Morris Mano
- Computer System Architecture. 3e
- Course Outcome: After completion of the Course
- Students will be able to: No Course Outcomes RBT Level* 01 Demonstrate the architectural features in the GPU and MIC hardware accelerators
- UN 02 Implement high-performance versions of standard single-threaded algorithms
- AP 03 Develop programs to extract maximum performance in a multicore
- shared memory execution environment processor AP 04 Examine cache coherence and consistency problems in multiprocessors, and their existing solutions
- AN Wef-AY-2021-22 05 Assess the large scale parallel programs on tightly coupled parallel systems using the message passing paradigm
- EL *RM: Remember
- UN: Understand
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