Digital VLSI Design & Verification- I Frontend (Elective)
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Follow on Instagram for UpdatesDigital VLSI Design & Verification- I Frontend (Elective) Syllabus — Unit-wise Content
The official GTU curriculum for Digital VLSI Design & Verification- I Frontend (Elective) (subject code 3715204) as prescribed for EAC( · Semester 1 divides the course into 4 units, covering 41 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (3715204)Unit 1 Basics of Semiconductor Devices
- Recap of semiconductor theory
- P-N junction & BJT structure and principle of operation
Unit 2 Introduction - Levels of IC design – Digital circuit fundamentals
- Concept of IC
- IC structure
- History and evolution of the IC industry
- Moore’s Law
- Design economics - Nonrecurring engineering costs (NRE) & Recurring costs
- Yield & Technology scaling
- System level Design
- Top down design
- Bottom up design
- Back end design
- Design abstraction levels
- Behavior Level
- Register-Transfer Level (RTL)
- Logic Level
- Circuit Level
- Component level
- Examples of Domains and its Abstraction Levels
- CMOS logic gates
- Combinational circuits
- Sequential circuits, FSM
Unit 3 Design Flow
- Design flow: Frontend – Marketing Requirements
- Design specification
- Verification plan
- RTL description
- Functional verification
- Backend – Partitioning
- Floor planning
- Placement, CTS, Routing & layout generation
- layout verification
- Foundry – Fabrication Introduction to Testing – Need for testing
- manufacturing test
- design for test
- chip-level test
- system-level test
- test generation & fault models Introduction to System on chip (Soc) design - Soft cores
- Firm cores
- Hard cores
- Study of AMBA AXI4 protocol
Unit 4 IC Design techniques & options, CAD design, Design challenges
- Structured design techniques: hierarchy
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