Power Efficient VLSI Design
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Follow on Instagram for UpdatesPower Efficient VLSI Design Syllabus — Unit-wise Content
The official GTU curriculum for Power Efficient VLSI Design (subject code 2744202) as prescribed for EAC( · Semester 4 divides the course into 7 units, covering 39 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.
Download the official syllabus PDF (2744202)Unit 2 Need for Low Power VLSI Design
- Sources of Power dissipation on Digital Integrated circuits
- Emerging Low Power Approaches
- Physics of Power dissipation in CMOS Devices
- Device and Technology Impact on low Power designs
Unit 3 Dynamic dissipation in CMOS
- Transistor sizing and gate oxide thickness
- impact of technology Scaling
- technology and device innovation
Unit 4 Power estimation
- Simulation Power analysis SPICE circuit simulators
- Gate Level Logic simulation
- Capacitive power estimation
- static state power
- gate level capacitance estimation
- Architecture level analysis
- Data correlation analysis in DSP System
- Montecarlo Simulation
- Probabilistic Power Analysis: Random Logic Signals
- Probability and frequency
- Probabilistic Power Analysis techniques
- Signal entropy
Unit 5 Low Power Design
- Circuit level: Power consumption in circuits
- Flip-flops and latches design
- High capacitance nodes
- low power digital cells library logic level: Gate reorganization
- signal gating
- logic encoding, and state machine encoding
- pre-computation logic
Unit 6 Low Power Architecture and Systems
- Power and Performance Management
- Switching activity reduction
- parallel architecture with voltage reduction
- flow graph transformation
- low power arithmetic components
- low power memory design
Unit 7 Low power Clock Distribution
- Power dissipation in clock distribution
- single driver Vs distributed buffers
- Zero skew Vs tolerable skew
- chip and package co design of clock network
Unit 8 Algorithm and architected level methodologies
- design flow
- Algorithm level analysis and optimization
- Architectural level estimation and synthesis
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