Computer Organization & Architecture

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COMPUTER ORGANIZATION & BE05000511
FREE PDF BE05000511
Code: BE05000511 Credits: 2 Semester 5 Aero

Computer Organization & Architecture

Get the full GTU study material, English & Gujarati textbook PDFs, syllabus curriculum, and solved previous year question papers.

Computer Organization & Architecture Syllabus — Unit-wise Content

The official GTU curriculum for Computer Organization & Architecture (subject code BE05000511) as prescribed for Aero · Semester 5 divides the course into 9 units, covering 64 listed topics. The unit-wise breakdown below is read from the GTU syllabus document for this subject code, so you can check what the course actually covers before deciding which papers to attempt.

Download the official syllabus PDF (BE05000511)

Unit 1 Computer Data Representation

5 lecture hours

  • Basic computer data types
  • Fixed point representation
  • Register Transfer and Micro-operations: Floating point representation
  • Register Transfer language
  • Register Transfer
  • Bus and Memory Transfers (Tree- State Bus Buffers
  • Memory Transfer)
  • Arithmetic Micro Operations
  • Logic Micro- Operations
  • Shift Micro-Operations
  • Arithmetic logical shift unit

Unit 2 Basic Computer Organization and Design

4 lecture hours

  • Instruction codes
  • Computer registers
  • computer instructions
  • Timing and Control
  • Instruction cycle
  • Memory-Reference Instructions
  • Input-output and interrupt
  • Complete computer description
  • Design of Basic computer
  • Design of Accumulator Unit

Unit 3 Assembly Language Programming

6 lecture hours

  • Machine Language
  • Assembly Language Programming: Arithmetic and logic operations
  • looping constructs

Unit 4 Micro programmed Control Organization

4 lecture hours

  • Control Memory
  • Address sequencing
  • Micro program example
  • Design of Control Unit

Unit 5 Central Processing Unit

5 lecture hours

  • General Register Organization
  • Stack Organization
  • Instruction format
  • Addressing Modes
  • Data transfer and manipulation
  • Program control
  • Reduced Instruction Set Computer (RISC) & Complex Instruction Set Computer (CISC)

Unit 6 Pipeline And Vector Processing

5 lecture hours

  • Flynn's taxonomy
  • Parallel Processing
  • Arithmetic Pipeline
  • RISC Pipeline
  • Vector Processing
  • Array Processors

Unit 7 Computer Arithmetic

5 lecture hours

  • Addition and subtraction
  • Multiplication Algorithms (Booth Multiplication Algorithm)
  • Division Algorithms
  • Floating Point Arithmetic operations
  • Decimal Arithmetic Unit

Unit 8 Input-Output Organization

5 lecture hours

  • Input-Output Interface
  • Asynchronous Data Transfer
  • Modes Of Transfer
  • Priority Interrupt, DMA, Input-Output Processor (IOP)
  • CPUIOP Communication
  • Serial communication

Unit 9 Memory Organization

  • Memory Hierarchy
  • Main Memory
  • Auxiliary Memory
  • Associative Memory
  • Cache Memory
  • Virtual Memory. 6 Program Name: Bachelor of Engineering Level: UG Branch: ALL (Except Electronics and Communication Engineering and Allied Branches) Subject Code: BE05000511 Subject Name: Computer Organization & Architecture This syllabus is mapped with following United Nation’s Sustainable Development Goals: SDG 4 - Quality Education
  • SDG 8 - Decent Work and Economic Growth
  • SDG 9 - Industry
  • Innovation and Infrastructure
  • SDG 12 - Responsible Consumption and Production
  • SDG 13 -Climate Action Relevant BIS standards: IS 13252 (Part 1) – Safety of Information Technology Equipment IS/IEC 60950-1 – IT Equipment Safety IS/IEC 62368-1 – Audio/Video
  • IT & Communication Equipment Safety IS 14700 Series – Electromagnetic Compatibility (EMC) IS/IEC 61000 Series – EMC Standards IS 16603 – Data Center Infrastructure Requirements Also explore other relevant Indian and international standards

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